The present invention relates generally to graphics systems, and more particularly to several new powerful shader program instructions.
A computer forms images for display on a monitor by combining geometries or primitives such as lines, triangles, and stripes with associated textures. In general, a graphics processor receives primitives and textures, and from them determines the color intensity of individual pixels on the monitor.
More specifically, the received primitives and textures are processed by the graphics processor during one or more passes through a graphics pipeline referred to as a GPU pass. During each pass, primitives are converted by a rasterizer into fragments, which are then combined with their associated textures by a shader circuit. After shader processing is complete, the shaded fragments are output to a raster operations circuit, which generates pixels for display. Following this, the graphics pipeline is “flushed ” or cleared. During a following GPU pass, data stored during an earlier GPU pass may be read as a texture and used by the shader in fragment processing.
A recent major innovation in shader development has been the invention of a shader capable of running shader programs. This innovation has been made by NVIDIA Corporation of Santa Clara, Calif. A programmable shader receives the fragments and textures, often in the form of a “pixel quad ” (four pixel 's worth of information) and runs a shader program on that information to generate shaded fragments. A shader program may be loaded into the graphics processor, for example by a driver.
Currently, a shader cannot write data directly to the frame buffer. Rather, fragment processing is completed by the shader, and shaded fragments are provided to the raster operations circuit. The raster operations circuit then writes data to the frame buffer memory, which can be read by the shader as textures during a later GPU pass. This isolation increases the number of GPU passes required to generate a complete pixel.
Accordingly, what is needed are circuits, apparatus, and methods that enable a shader to write and read data from the frame buffer memory during an individual GPU pass.